English Intern
    Lehrstuhl für Informatik V - Technische Informatik

    Konferenzen

    C.Mühlberger On the Improvement of a Self-Organized MAC Protocol for Multi-Hop Wireless Sensor Networks 11. Fachgespräch Sensornetze, FGSN 2012

    A.Runge, M.Baunach Precise Self-Calibration of Ultrasound Based Indoor Localization Systems IPIN, Guimaraes, 2011

    A.Runge, M.Baunach, R.Kolla Distribute & Erase, a Self-Calibration Algorithm for Ultrasound Based Localization Systems 10. Fachgespräch Sensornetze, FGSN 2011

    C.Mühlberger, T.Schäfer SuperG: A Multi-Radio Architecture to interconnect multiple Wireless Sensor Networks 10. Fachgespräch Sensornetze, FGSN 2011

    Ch.Appold Improving BDD Based Symbolic Model Checking with Isomorphism Exploiting Transition Relations GandALF, Minori 2011

    Ch.Appold Symbolic Model Checking with Isomorphism Exploiting Transition Relations MBMV, Oldenburg 2011

    M.Baunach CoMem: Cooperative Memory Management for Real-Time Operation within Reactive Sensor/Actor Networks RTNS, Peking 2010

    Ch.Appold Efficient Symmetry Reduction and the Use of State Symmetries for Symbolic Model Checking GandALF, Minori 2010

    M.Baunach Collaborative Memory Management for Reactive Sensor/Actor Systems SenseApp, Denver 2010

    C.Mühlberger Desynchronization in Multi-Hop Topologies: A Challenge 9. Fachgespräch Sensornetze, FGSN 2010

    M.Baunach Dynamic Memory Management for Resource Constrained Sensor/Actor Systems 9. Fachgespräch Sensornetze, FGSN 2010

    Ch.Appold An Algorithm for Fast Symmetry Reduction in Symbolic Model Checking 9. Fachgespräch Sensornetze, FGSN 2010

    M.Baunach pVoted: A Progressive On-Line Algorithm for Robust Real-Time Localization and Tracking in spite of Faulty Distance Information International Conference on Indoor Positioning and Indoor Navigation (IPIN), Zürich, September 2010

    Ch.Appold Using State Symmetries to Speed up Symmetry Reduction in Model Checking SymCon'09 Lissabon 2009

    M.Baunach Dynamic Hinting: Real-Time Resource Management in Wireless Sensor/Actor Networks 15th IEEE RTCSA, Beijing, August 2009

    Ch.Appold Reliable Model Checking for WSNs 8. Fachgespräch Sensornetzwerke, FGSN 2009

    C.Mühlberger Energetic and Temporal Analysis of a Desynchronized TDMA Protocol for WSNs 8. Fachgespräch Sensornetzwerke, FGSN 2009

    M.Baunach Priority aware Resource Management for Real-Time Operation in Wireless Sensor/Actor Networks 8. Fachgespräch Sensornetzwerke, FGSN 2009

    M.Baunach, C.Mühlberger, Ch.Appold Enabling Real-Time in WSN Applications EWSN 2009 Cork, February 2009

    M.Baunach Ghost: Software and Configuration Distribution for Wireless Sensor/Actor Networks 7. Fachgespräch Sensornetzwerke, FGSN 2008, pp. 81-84

    C.Mühlberger, M.Baunach Tab WoNS: Calibration Approach for WSN based Ultrasound Localization Systems 7. Fachgespräch Sensornetzwerke, FGSN 2008, pp. 41-44 

    M.Baunach Speed, Reliability and Energy Efficiency of HashSlot Communication in WSN Based Localization Systems EWSN 2008 Bologna, January 2008

    M.Baunach, R.Kolla, C.Mühlberger Beyond Theory: Development of a real world localization application as low power WSN Second IEEE International Workshop on Practical Issues in Building Sensor Network Applications, SenseApp 2007

    M.Baunach, R.Kolla, C.Mühlberger A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot Second IEEE International Workshop on Practical Issues in Building Sensor Network Applications, SenseApp 2007

    M.Baunach, R.Kolla, C.Mühlberger Introduction to a Small Modular Adept Real-Time Operating System 6. Fachgespräch Sensornetzwerke, FGSN 2007, pp. 1-4 

    M.Baunach, R.Kolla, C.Mühlberger SNoW5: A versatile ultra low power modular node for wireless ad hoc sensor networking 5. GI/ITG KuVS Fachgespräch „Drahtlose Sensornetze“, FGSN 2006, pp. 55-59

    F.Wolz, R.Kolla A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, pp. 997-1006

    F.Wolz, R.Kolla Bubble Partitioning for LUT-based Sequential Circuits 11th International Conference on Field-Programmable Logic and Applications, FPL 2001, pp. 336-345

    F.Wolz, R.Kolla A New Floorplanning Method for FPGA Architectural Research 10th International Conference on Field-Programmable Logic and Applications, FPL 2000, pp. 432-442

    R. Kolla, A. Vodopivec, J. Wolff v. Gudenberg Splitting Double-Precision FPUs for Single-Precision Interval Arithmetic Workshop zur Architektur von Rechensystemen, ARCS 1999, pp. 5-16 

    W.Nöth, R.Kolla Spanning Tree-based State Encoding for Low-Power Dissipation Design Automation and Test Conference in Europe, DATE 1999, pp. 168-174 

    F.Duckstein, R.Kolla Ray Tracing of Parametric Surfaces Based on Andaptive Simplicial Complexes 7th International Conference in Central Europe on Computer Graphics, Visualization and Interactive Digital Media, WSCG 1999, pp. 63-70

    U.Hinsberger, R.Kolla Boolean Matching for Large Libraries 35th Design Automation Conference, DAC 1998, pp. 206-211

    F.Duckstein Extension of Validity Calculation to Moving Objects within a Virtual Reality System Using Frame-to-Frame Coherence 6th Internationl Conference in Central Europe on Computer Graphics and Visualization, WSCG 1998, pp.81-88 

    O.Springauf, R.Kolla PACE: Processor Architectures for Circuit Emulation Workshop on Parallel and Distributed Processing, IPPS/SPDP 1998, pp. 105-110

    W.Nöth, R.Kolla Node Normalization and Decomposition in Low-Power Technology Mapping International Symposium on Low Power Electronics and Design, 1997, pp. 275-280

    U.Hinsberger, R.Kolla, M.Wild A Parallel Hybrid Approach to Hard Optimization Problems Workshop zur Architektur von Rechensystemen, ARCS 1997, pp. 201-210

    U.Hinsberger, R.Kolla, W.Nöth TROY - A Tree-based Approach to Logic Synthesis and Technology Mapping 6th Great Lakes Symposium on VLSI, Ames 1996, pp. 188-193

    U.Hinsberger, R.Kolla Performance-Optimal Technology Mapping for Single Output Cells 5th Great Lakes Symposium on VLSI, Buffalo 1995, pp. 14-19

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