Intern
29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)

Programm


Keynote: Machine Learning for System-Level Modeling

Speaker: Prof. Andreas Gerstlauer, The University of Texas at Austin

Abstract:

Applications of machine learning (ML) techniques to design problems has seen a lot of excitement and promise at lower levels of abstraction. By contrast, corresponding approaches at the system level have been relatively less explored. In this talk, we will discuss applications of ML for system-level design. In particular, fast and accurate models that can drive rapid, early design space exploration, co-design and co-optimizations are critical for any systematic and well-defined design process. Recently, ML-based, predictive models have emerged to bridge the gap between traditional slow simulation-based methodologies and inaccurate analytical models. Such models are trained to learn and predict system behavior, performance and power consumption across abstraction levels, across heterogeneous hardware/software components and across time. We will discuss solutions, challenges and opportunities for ML-based cross-layer, cross-platform and cross-temporal modeling in the talk. Furthermore, we will demonstrate how such ML-based models can be leveraged to drive system architecture co-design and exploration, system programming and proactive runtime management.

Bio:

Andreas Gerstlauer is a Cullen Trust for Higher Education Endowed Professor and Associate Chair for Academic Affairs in the Electrical and Computer Engineering (ECE) Department at The University of Texas at Austin. He received his Ph.D. degree in Information and Computer Science (ICS) from the University of California, Irvine (UCI) in 2004. Prior to joining UT Austin in 2008, he was an Assistant Researcher in the Center for Embedded Computer Systems (CECS) at UC Irvine, leading a research group to develop electronic system-level design tools. Dr. Gerstlauer is co-author on 3 books and more than 150 conference and journal publications. His work was recognized with the 2024 HASP, 2021 MLCAD, 2016 DAC and 2015 SAMOS best paper awards, several best paper nominations from, among others, DAC, DATE, FCCM and HOST conferences, and as a 2021 IEEE HSTTC Top Pick in Hardware and Embedded Security and one of the most influential contributions in 10 years at DATE in 2008. He is the recipient of a 2016-2017 Humboldt Research Fellowship. He serves or has served as an Senior, Associate and Special Issue Editor for ACM TECS and TODAES journals as well as General or Program Chair for major international conferences such as ESWEEK, MEMOCODE, CODES+ISSS and SAMOS.  His research interests include system-level design automation, system modeling, design languages and methodologies, and embedded hardware and software synthesis.


Dienstag 17.03.2026

09:00 - 09:15 Eröffnung der Tagung
09:15 - 10:15 Keynote: Prof. Andreas Gerstlauer
10:15 - 11:15 Session 1: Accelerators
  Modeling and Mapping of Regular Nested Loops on Processor Arrays: CGRAs vs. TCPAs
  GPCC: Grid of Processing Cells Compiler with Pareto-Optimal Parallel Exploration
  Transparent integration of FPGA hardware accelerators into IEC 61499 applications
11:15 - 11:45 Pause
11:45 - 12:45 Session 2: AI and Data-Driven Approaches
  AI-based abstraction of test programs
  A Formal Description of Communication Protocols Using Petri-Nets
  Data-Driven Identification of Hybrid Systems using Genetic Programming
12:45 - 13:45 Mittagessen
13:45 - 14:45 Session 3: Simulation
  Accelerating Accurate DRAM Simulation Using Dynamic Binary Instrumentation For Online Trace Generation
  A Simulation-Based Analysis of Execution Time Distributions and Cache Performance
  Using Virtual Prototypes for Causal Fault Explanation at System Level
14:45 - 15:15 Pause
15:15 - 16:35 Session 4: RISC-V
  TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture
  Truly Scalable Grids of RISC-V Processors with Local Memories
  FastISS-Enhanced RISC-V VP++: Latest Results in High-Performance Interpreter-Based Simulation
  Instruction Set Simulator based exploration of tightly coupled RISC-V Hardware Acceleration for HQC Post-Quantum Cryptography Algorithm
16:35 - 17:05 Sitzung der GMM/ITG/GI-Fachgruppen 3 und 4
18:00 - 19:00 Stadtführung durch Würzburg
19:00 Abendessen im Würzburger Ratskeller

Mittwoch 18.03.2026

09:15 - 10:55 Session 5: Modeling and Benchmarking
  To Count or Not to Count: On the Usage of Performance Counter Metrics for Host to Embedded GPU Performance Estimation
  Model-Driven Generation of Asynchronous Circuits focusing on RISC-V Processors
  Hardware Agnostic Energy Benchmarking For Machine Learning
  Decompositional Abstraction for Composite Hierarchical Systems via Hybrid Unrolling and Nested Derivation (DACHSHUND)
  On the Origins of Self-Explainability in Cyber-Physical Systems: Model-Based and Data-Driven Approaches
10:55 - 11:10 Pause
11:10 - 12:50 Session 6: Security and Verification
  Integration of automated security analysis into the early stages of model-based development for HW/SW of IoT systems
  SCVPI*: A Reusable PyUVM-Based Verification Framework for RTL and SystemC Models
  Interactive Verification Using Averest: The Basic Theorem Proving Infrastructure
  Okapi: Efficiently Safeguarding Speculative Data Accesses in Sandboxed Environments
  Enabling Power Side-Channel Attack Simulation in Gem5
12:50 - 13:00 Abschluss der Tagung
13:00 - 14:00 Mittagessen