Open Theses
If you are interested in one of the topics, feel free to contact the corresponding supervisors.
Modeling Non-Volatile Main Memories in DRAMSys
Type:
Bachelor/Master Thesis
Summary:
DRAM faces significant scalability issues as power drastically increases while capacitors in the memory cells reach physical limitations, thus falling behind modern requirements in terms of storage density.
Byte-addressable Non-Volatile Memory technologies such as Phase Change Memory (PCM) or Resistive RAM (RRAM) can promise to become a high-density, low-leakage alternative, however, endurance limitations as well as significantly higher latencies and energy consumptions during write operations are hindering NVM from fully replacing DRAM.
As these devices have not reached full-production scale, with the now-discontinued Intel Optane [1] being the notable exception, modeling these technologies and investigating their use on a system-level through simulation and virtual prototyping is essential.
The key challenges in the simulation of NVMs lie in a) Finding suitable device-level parameters and b) Understanding and modeling adjustments necessary to traditional memory interfaces (e.g., DDR5)
While tools such as NVSim [2] and NVMain [3] attempt to provide a solution, they have become outdated compared to other memory simulators, making full-system simulations complicated and potentially inaccurate.
Therefore, in this thesis, the memory simulator DRAMSys [4] is to be extended for the purpose of modeling NVM main memories. This requires adjustments to the protocols included in the simulator, understanding NVM-based architectures, as well as a deep-dive into current device-level trends in order to determine the expected power and latency domains.
Supervisors:
Nils Wilbert and Prof. Matthias Jung
Links:
Accelerating Memory Subsystem Simulation Using Elastic Traces Generated via Dynamic Binary Instrumentation
Type:
Master Thesis
Summary:
The performance of modern computing systems is increasingly constrained by the memory subsystem, particularly DRAM, leading to what is commonly referred to as the "memory wall". To address this challenge, simulation is essential for exploring more efficient memory configurations tailored to specific applications. However, traditional simulation approaches face significant limitations: fixed-time trace-based simulations lack accuracy because they fail to account for the dynamic behavior of memory, while full-system simulations, though accurate, are prohibitively slow due to the need to simulate out-of-order (O3) cores.
This thesis proposes a novel approach to accelerate O3 core simulation by leveraging elastic traces, inspired by existing work such as [1]. Unlike previous methods that rely on O3 core simulations using gem5 to generate traces, this approach utilizes dynamic binary instrumentation (DBI).
The goal of this thesis is to develop a DBI tool using DynamoRIO (or another open-source framework) to generate elastic traces and a special trace player, that plays back these elastic traces to the DRAM simulator DRAMSys.
Supervisors:
Derek Christ and Prof. Matthias Jung
Links:
1. R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, and N. When, “Exploring System Performance using Elastic Traces: Fast, Accurate and Portable,” in 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016, pp. 96–105. doi: 10.1109/SAMOS.2016.7818336.
DRAM Simulation with Loosely Timed (LT) Models
Type:
Bachelor/Master Thesis
Summary:
This topic investigates whether DRAM systems can be simulated efficiently using Loosely Timed (LT) models while maintaining accuracy comparable to Approximately Timed (AT) simulations. Recent work such as BusyMap [1] used special data structures to capture interconnect contention with higher precision in LT simulations. The goal is to analyze, design, and evaluate methods that enable accurate yet computationally efficient DRAM simulation at the LT abstraction level.
Supervisors:
Derek Christ and Prof. Matthias Jung
Links:
1. E. M. Arasteh, V. Govindasamy, and R. Dömer, “BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain: IEEE, Mar. 2024, pp. 1–6. doi: 10.23919/DATE58400.2024.10546686.
Development of a Software for Field Field Strength Meter Calibration
Type:
Bachelor Thesis / Project Work
Summary:
In many countries, regulations limit the electromagnetic field strength around licensed amateur radio stations to ensure public safety. When dealing with complex station setups and environmental conditions, measurement results are often the only possible evidence. Therefore, the proper calibration of used field strength meters is essential. This project aims to update an existing Windows software [1] and develop a new calibration setup based on Linux. The software should be platform-independent, built using C++ or Rust with a focus on Test-Driven Development and Documentation. It should communicate with measurement equipment via IEEE488 and USB, while also recording a video stream of the measurements. Remote control functionality is desired, with a split between server and host seeming like a reasonable approach. Finally, the software should output measurement results in a spreadsheet format. Once the new software is set up, measurements will be taken and compared to those obtained with the old legacy system.
Supervisor:
Links:
Development of Software for ADALM Pluto SDR
Type:
Bachelor or Master Thesis
Summary:
The objective of this project is to develop a Software-Defined Radio (SDR) application for controlling the ADALM Pluto FPGA SDR plattform [2], manufactured by Analog Devices. The software will provide functionalities for both signal reception (RX) and transmission (TX). Moreover, it will include a waterfall diagram and spectrum view, along with the capability to demodulate and modulate Single Sideband (SSB) signals [3]. Additionally, the software will support the connection to the Pluto via ethernet and audio input and output via the computer's sound card. The implementation will be based on the Qt framework, with [1] serving as the initial reference. The primary purpose of this SDR application is to establish communication with the geostationary satellite QO-100.
Supervisors:
Prof. Matthias Jung and Prof. Guido Dietl
Links:
