Publications
2023[ to top ]
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Automatic DRAM Subsystem Configuration with irace in Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO) (2023).
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A Precise Measurement Platform for LPDDR4 Memories in ACM/IEEE International Symposium on Memory Systems (MEMSYS 2023) (2023).
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Neues Ausbildungsmaterial für alle Klassen in Amateurfunk-Tagung München (2023).
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2022[ to top ]
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Amateurfunkprüfung: Zwischenstand neuer Fragenkatalog in Weinheimer UKW-Tagung (2022).
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Split’n’Cover: ISO26262 Hardware Safety Analysis with SystemC in Springer LNCS International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS) (2022).
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Unveiling the Real Performance of LPDDR5 Memories in ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022) (2022).
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A Framework for Formal Verification of DRAM Controllers in ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022) (2022).
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DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses in Springer, International Journal of Parallel Programming (IJPP) (2022).
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A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference in Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) (2022).
2021[ to top ]
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A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs in 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021) (2021).
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Exploration of DDR5 with the Open Source Simulator DRAMSys in IEEE/VDE Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen MBMV (2021).
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The Dynamic Random Access Memory Challenge in Embedded Computing Systems (Book Chapter in: A Journey of Embedded and Cyber-Physical Systems: Essays Dedicated to Peter Marwedel on the Occasion of His 70th {B}irthday) (2021). Springer International Publishing.
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A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation in IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
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Online Working Set Change Detection with Constant Complexity in ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021) (2021).
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An LPDDR4 Safety Model for Automotive Applications in ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021) (2021).
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SEC-Learn: Sensor Edge Cloud for Federated Learning in Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI) (2021).
2020[ to top ]
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The gem5 Simulator: Version 20.0+ (2020).
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Fast and Accurate DRAM Simulation: Can we Further Accelerate it? in 2020 Design, Automation Test in Europe Conference Exhibition (DATE) (2020). 364–369.
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Moderne Speicherarchitekturen für leistungsfähige Infotainmentsysteme und autonomes Fahren in ATZelektronik (2020). 15(11) 16–21.
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An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices in International Symposium on Memory Systems (MEMSYS 2020) (2020).
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A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions in International Symposium on Memory Systems (MEMSYS 2020) (2020).
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Efficient Generation of Application Specific Memory Controllers in International Symposium on Memory Systems (MEMSYS 2020) (2020).
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eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex in Journal of Signal Processing Systems (2020).
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DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator in International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS) (2020).
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System Simulation with PULP Virtual Platform and SystemC in International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO) (2020).
2019[ to top ]
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Fast Validation of DRAM Protocols with Timed Petri Nets in Proceedings of the International Symposium on Memory Systems, MEMSYS ’19 (2019). 133–147.
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Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling in Proceedings of the 48th International Conference on Parallel Processing: Workshops, ICPP 2019 (2019).
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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing in Embedded Computer Systems: Architectures, Modeling, and Simulation, D. N. Pnevmatikatos, M. Pelcat, M. Jung (eds.) (2019). 429–441.
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3D Stacked DRAM Memories (Book chapter in the Handbook of 3D {I}ntegration) (2019). (Vol. 4) Wiley-VCH.
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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM in 2019 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (2019).
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NNDRAM: A Deep In-DRAM Computing Architecture for Neural Network Processing in IEEE International Symposium on Circuits and Systems (ISCAS) (2019).
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Speculative Temporal Decoupling Using fork() in IEEE Conference on Design, Automation and Test in Europe (DATE) (2019). 1721–1726.
2018[ to top ]
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Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes in Software Architecture, C. E. Cuesta, D. Garlan, J. Pérez (eds.) (2018). 115–130.
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BOSMI: A Framework for Non-intrusive Monitoring and Testing of Embedded Multithreaded Software on the Logical Level in Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS ’18 (2018). 131–138.
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A Model-Based Safety Analysis of Dependencies Across Abstraction Layers in Computer Safety, Reliability, and Security, B. Gallina, A. Skavhaug, F. Bitsch (eds.) (2018). 73–87.
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An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs in IEEE Conference Design, Automation and Test in Europe (DATE) (2018).
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Driving into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving in Proceedings of the International Symposium on Memory Systems, MEMSYS ’18 (2018). 377–386.
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A Framework for Non-Intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration in The 18th International Conference on Runtime Verification (RV 2018) (2018).
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Efficient Coding Scheme for DDR4 Memory Subsystems in ACM International Symposium on Memory Systems (MEMSYS 2018) (2018).
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The Role of Memories in Transprecision Computing in IEEE International Symposium on Circuits and Systems (ISCAS) (2018).
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Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property in IEEE Conference Design, Automation and Test in Europe (DATE) (2018).
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Driving Against the Memory Wall: The Role of Memory for Autonomous Driving in Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE) (2018).
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A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs in IEEE Design & Test (2018). 35(1) 7–15.
2017[ to top ]
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3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems in International Journal of Parallel Programming (2017). 1–41.
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A Bank-Wise DRAM Power Model for System Simulations in Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO ’17 (2017). 5:1–5:7.
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System-Level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures (2017). University of Kaiserslautern.
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Using Run-Time Reverse-Engineering to Optimize DRAM Refresh in International Symposium on Memory Systems (MEMSYS17) (2017).
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Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact in International Symposium on Memory Systems (MEMSYS17) (2017).
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DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool in International Journal of Parallel Programming (2017). 45(6) 1566–1591.
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A Platform to Analyze DDR3 DRAM’s Power and Retention Time in IEEE Design & Test (2017). 34(4) 52–59.
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A New State Model for DRAMs Using Petri Nets in 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (2017). 221–226.
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System Simulation with gem5 and SystemC: The Keystone for Full Interoperability in 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (2017). 62–69.
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Supervised Testing of Concurrent Software in Embedded Systems in 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (2017). 233–238.
2016[ to top ]
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A cross layer approach for efficient thermal management in 3D stacked SoCs in Microelectronics Reliability (2016). 61 43–47.
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ConGen: An Application Specific DRAM Memory Controller Generator in Proceedings of the Second International Symposium on Memory Systems, MEMSYS ’16 (2016). 257–267.
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A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D--Stacked Architecture in Journal of Signal Processing Systems (2016). 1–15.
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Exploring System Performance using Elastic Traces: Fast, Accurate and Portable in IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece (2016).
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A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration in International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016) (2016).
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Efficient Reliability Management in SoCs - An Approximate DRAM Perspective in 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (2016).
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Software Architectures for Embedded Software Systems (2016). Distance and Independent Studies Center (DISC) University of Kaiserslautern.
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Reverse Engineering of DRAMs: Row Hammer with Crosshair in International Symposium on Memory Systems (MEMSYS 2016) (2016).
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Approximate Computing with Partially Unreliable Dynamic Random Access Memory - Approximate DRAM in Proceedings of the 53rd Annual Design Automation Conference, DAC ’16 (2016). 100:1–100:4.
2015[ to top ]
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Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs in Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE) (2015).
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Thermal Aspects and High-level Explorations of 3D stacked DRAMs in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2015).
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Reliability and Thermal Challenges in 3D Integrated Embedded Systems in 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands. (2015).
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Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs in 1st International Symposium on Memory Systems (MEMSYS 2015) (2015).
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DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework in IPSJ Transactions on System LSI Design Methodology (T-SLDM) (2015).
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A Custom Computing System for Finding Similarties in Complex Networks in Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2015). 262–267.
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A High-Level DRAM Timing, Power and Area Exploration Tool in Embedded Computer Systems Architectures Modeling and Simulation (SAMOS) (2015).
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Coupling gem5 with SystemC TLM 2.0 Virtual Platforms in gem5 User Workshop, International Symposium on Computer Architecture (ISCA) (2015).
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Virtual Development on Mixed Abstraction Levels: an Agricultural Vehicle Case Study in Synopsys Usergroup Conference (SNUG) (2015).
2014[ to top ]
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Thermal Modelling of 3D Stacked DRAM with Virtual Platforms in Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14) (2014). (Vol. 10)
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Optimized active and power-down mode refresh control in 3D-DRAMs in Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on (2014). 1–6.
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Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-Wise Refresh in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 (2014). 1–4.
2013[ to top ]
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Virtual Platforms for Fast Memory Subsystem Exploration Using gem5 and TLM2.0 in Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13) (2013). (Vol. 9) 153–156.
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TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration in Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO ’13 (2013). 5:1–5:6.
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Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms in Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany. (2013).
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Virtual Platforms for Fast Exploration of Computing Systems in Finance in Young Researcher Symposium, YRS 2013. Proceedings (2013). 18–23.
2012[ to top ]
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A Scalable Multi-Core ASIP Virtual Platform For Standard-Compliant Trellis Decoding in Synopsys User Group Conference (SNUG) (2012).
2011[ to top ]
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Energy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing in Knowledge-Based and Intelligent Information and Engineering Systems, A. König, A. Dengel, K. Hinkelmann, K. Kise, R. J. Howlett, L. C. Jain (eds.) (2011). (Vol. 6884) 177–186.
